1. Field of the Invention
The present invention relates in general to a self-calibrating strobe signal generator capable of producing edges in two strobe signals with an accurately adjustable delay between them suitable for use in a built-in self-test circuit for measuring path delays in an IC.
2. Description of Related Art
IC designers typically place timing constraints on various signal paths within an IC specifying that a state change in a signal path input signal is to produce a state change in a signal path output signal within some specified maximum target delay. Test equipment can test whether the delay between state changes in a signal path's input and output signals is within a such a target delay by changing the state of a signal at the path input and thereafter sampling the signal at the path output with the specified target delay to determine whether the path output signal has changed state. However, in many cases external test equipment capable of testing path delays will not be able to directly access the input and/or the output terminal of a signal path within an IC to be tested. One solution to that problem is to incorporate a built-in self-test (BIST) circuit directly into the IC providing circuits for measuring the path delay. U.S. Pat. No. 6,058,496 issued May 2, 2000 to Gillis et al describes one such BIST circuit.
FIG. 1 depicts in simplified block diagram form a prior art BIST circuit 10 incorporating principles taught by Gillis et al. The IC in which BIST circuit 10 is embedded includes an input/output (I/O) driver 14 and a receiver 15 linked to one of the IC's I/O pads 16, and the path delay to be measured extends from the input of driver 24 to the output of receiver 25, neither of which is accessible to external test equipment. Various “core logic” circuits internal to the IC normally use driver 14 and receiver 15 to communicate with external circuits but during testing, BIST circuit 10 connects driver 14 and receiver 15 to a pair of latches 24 and 25.
To measure the delay though path 12, a controller 27 signals a multiplexer 20 within BIST circuit 10 to pass a clock signal A through a clock tree 22 (a buffered signal path) to provide a strobe signal B for clocking latch 24 at the input of driver 14. Controller 27 sets the state of a signal DI at the input of latch 24 so that when strobe B clocks latch 24, the input of driver 14 changes state, for example, from a “0” to a “1”. When signal path 12 is functioning properly, the state change at the input of driver 14 causes the output signal DO of receiver 15 to change from a 0 to a 1 with a delay that is largely a function of the switching speeds of driver 14 and receiver 15. A programmable delay circuit 26 delays strobe signal B to produce a strobe signal C for clocking latch 25 at the output of receiver 15. The DO signal will be of state “1” immediately after strobe signal C clocks latch 25 if the delay through path 12 is less than the delay through programmable delay circuit 26. Otherwise, the DO signal will be of state “0” when the delay through path 12 is greater than the delay through programmable delay circuit 26.
To measure the delay though path 12, controller 27 iteratively adjusts the delay of programmable delay circuit 26 to find the largest delay for which the DO bit will be 0 immediately following the strobe signal C edge when the driver 14 input signal changes from a 0 to a 1 in response to a signal B edge. At that point, the delay through programmable delay circuit 26 will match the delay through path 12 within the timing resolution of delay circuit 26.
Controller 27 may then measure the delay through programmable delay circuit 26 to determine the delay through path 12. To do so, controller 27 sets multiplexer 20 to feed strobe signal C back to clock tree 22. Since clock tree 22 logically inverts its input to produce strobe signal B, the negative feedback path through multiplexer 20 causes strobe signals B and C to oscillate. With the delay though programmable delay circuit 26 set to match the delay though I/O cell 12, controller 27 counts a number of edges of the strobe signal C occurring during a predetermined number J of cycles of a reference clock signal (CLOCK) having known period. The count (COUNT1) is inversely proportional to the sum of delays through multiplexer 20, clock tree 22 and programmable delay circuit 26. Controller 27 also performs the same count operation while programmable delay circuit 26 is set for 0 delay to produce a second count (COUNT2) inversely proportional to the delay through multiplexer 20 and clock tree 22. From the COUNT1 and COUNT2 values, controller 27 calculates PROG_DELAY data of value proportional to the delay through programmable delay circuit 26 when set to match the delay through path 12 as follows:PROG_DELAY=(K/COUNT1)−(K/COUNT2)  [1]where K is a constant sufficiently larger than any possible value of COUNT1 or COUNT2 to ensure that PROG_DELAY data value will be greater than 0 and will have an adequately wide range over all possible combination of COUNT1 and COUNT2 values. Controller 27 then forwards the computed PROG_DELAY data to external equipment for computing the actual path delay through path 12 from the PROG_DELAY data given known values of K and J and the known period of the CLOCK signal.
BIST circuit 10 can also perform a “go/nogo” test of the delay through path 12 to determine whether the delay is higher or lower than a target delay referenced by TARGET_DELAY data supplied as input to the BIST circuit. To do so controller 27 sets the delay though programmable delay circuit 26 to match the target delay indicated by the TARGET_DELAY data. Thereafter, with multiplexer 20 set to select strobe signal A, the DO bit state following the strobe signal C edge will indicate whether the delay through path 12 is within the target delay. The DO bit is then provided to the external equipment.
To set delay circuit 26 so that its delay matches the specified target delay, controller 27 initially sets multiplexer 20 to select strobe signal C, sets delay circuit 26 for zero delay and then counts the number COUNT2 of edges of the C signal occurring during N cycles of the CLOCK signal. Controller 27 then increments the delay of programmable delay circuit 26, generates the COUNT1 data, and computes the PROG_DELAY data for the current programmable delay setting in accordance with equation [1] above. If the PROG_DELAY data is smaller than TARGET_DELAY, controller again increments the delay of programmable delay circuit 26, determines a COUNT1 value for that programmable delay, then re-computes PROG_DELAY and again compares it to TARGET_DELAY. Controller 27 continues to iteratively increase the programmable delay in this manner until the computed PROG_DELAY value reaches the TARGET_DELAY value. At that point the delay of programmable delay circuit will match the target delay for which path 12 is to be tested.
Note that much of BIST circuit 10 acts as a “self-calibrating strobe signal generator” for generating two strobe signals B and C with a B-to-C delay controlled by input TARGET_DELAY data. BIST circuit 10 is “self-calibrating” in the sense that it automatically measures and adjusts the B-to-C delay using the CLOCK signal period as a timing reference.
A BIST circuit is ideally small, fast and accurate. One drawback to BIST circuit 10 is that to evaluate equation [1] above during the self-calibration process controller 27 employs relatively complex logic, including an arithmetic logic unit (ALU) preferably capable of handling floating point divisions and subtractions. Such complex logic can consume substantial floor space within an IC and may require many clock cycles to perform the necessary calculations once the count data for those calculations has been acquired. The calculation process can therefore extend the time required to test path delays.
The calibration procedure can also be somewhat inaccurate when programmable delay circuit 26 provides substantial residual delay when nominally set for zero delay during the calibration process as is typically the case for conventional programmable delay circuits. Since equation [1] assumes the COUNT2 data value represents zero programmable delay and not a non-zero residual delay, the PROG_DELAY data controller 27 produces underestimates the actual programmable delay by the amount of that residual delay.
What is needed is a strobe signal generator suitable for use in a BIST circuit for providing strobe signals separated with an adjustable delay. The strobe signal generator should include a small self-calibration circuit for quickly and accurately measuring and adjusting the strobe delay without requiring an ALU or other complex data processing hardware.